Embodiments of the present disclosure generally relate to a precharge control device and a semiconductor device including the same, and more particularly to a technology for reducing the size of a region of a precharge circuit.
Generally, a memory cell array of a semiconductor memory device may be divided into multiple banks so that a plurality of memory banks can simultaneously work on different requests. For example, a precharge timing may vary depending on memory banks. The semiconductor memory device may perform a data write operation in response to a write command including an auto precharge command. Upon completion of the write operation, the semiconductor memory device may automatically disable word lines. The above-mentioned operations may be carried out by an auto-precharge control circuit contained in the semiconductor memory device.
If the write command including the auto-precharge command is input to the semiconductor memory device, the auto-precharge control circuit may automatically generate a precharge signal at a predetermined time after the write operation of target memory cells (or target memory bank) of the semiconductor memory device has been completed. As a result, a row activation circuit (or a row decoder) may disable word lines connected to the write-operation-completed memory cells (or memory bank) in response to the precharge signal.
An auto precharge involves individual bank precharging, and it is possible for each bank to have its own auto-precharge control circuit to generate an auto-precharge signal per bank. Assuming that the semiconductor memory device includes eight banks, if each bank has its own auto-precharge control circuit, the semiconductor memory device will need a total of eight auto-precharge control circuits, and this may lead to an increase in a size of the semiconductor memory device. Moreover, a space occupied by the auto-precharge control circuits increases as the number of banks increases.